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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. TPSM846C24 slvse06 ? january 2018 TPSM846C24 4.5-v to 15-v input, 0.5-v to 2-v output, 35-a power module 1 1 features 1 ? complete integrated 35-a power solution ? pin compatible with tpsm846c23 (pmbus) ? stackable up to 70 a with current sharing ? output voltage range 0.5 v to 2 v ? output voltage accuracy as tight as 0.5% ? 15 mm 16 mm footprint (6.4 mm maximum height) ? 300-khz to 1-mhz switching frequency ? synchronization to an external clock ? differential remote sense ? power-good output ? prebias output monotonic start-up ? fixed 3-ms soft-start / soft-stop time ? overcurrent protection ? operating ic junction range: ? 40 c to +125 c ? operating ambient range: ? 40 c to +105 c ? enhanced thermal performance: 8.7 c/w ? meets en55022 class a emissions ? create a custom design using the TPSM846C24 with the webench ? power designer 2 applications ? compact pci / pci express / pxi express ? broadband and communications infrastructure ? automated test and medical equipment ? dsp, fpga, and asic point-of-load applications 3 description the TPSM846C24 is a 35-a, fixed-frequency, step- down power module. the module incorporates the controller, power mosfets, inductor, and associated components into a rugged, thermally enhanced, surface-mount package. the user supplies the input and output capacitors along with a few other passive components to set the operating parameters of the module. two modules can be configured to work in parallel to provide up to a 70-a, two-phase power solution. the 15 mm 16 mm component footprint is easy to solder onto a printed circuit board and allows a compact, point-of-load design. device information (1) part number package body size (nom) TPSM846C24 mol (59) 15 mm 16 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. space space space simplified schematic efficiency vs output current output current (a) efficiency (%) 0 5 10 15 20 25 30 35 55 60 65 70 75 80 85 90 95 100 eff1 v out = 1.8 v v in = 5 v v in = 12 v TPSM846C24 vin pgnd v in vout vs+ diffo pgnd vs- agnd v out fb pgnd pgood r set en sync copyright ? 2018, texas instruments incorporated tools & software technical documents ordernow productfolder support &community
2 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 6 6.5 electrical characteristics ........................................... 6 6.6 switching characteristics .......................................... 8 6.7 typical characteristics (v in = 12 v) .......................... 9 6.8 typical characteristics (v in = 5 v) .......................... 10 7 detailed description ............................................ 11 7.1 overview ................................................................. 11 7.2 functional block diagram ....................................... 11 7.3 feature description ................................................. 12 7.4 device functional modes ........................................ 20 8 application and implementation ........................ 21 8.1 typical application .................................................. 21 9 power supply recommendations ...................... 24 10 layout ................................................................... 24 10.1 layout guidelines ................................................. 24 10.2 layout example .................................................... 25 10.3 package specifications ......................................... 26 10.4 emi ........................................................................ 26 10.5 mounting and thermal profile recommendation.. 28 11 device and documentation support ................. 29 11.1 device support ...................................................... 29 11.2 receiving notification of documentation updates 29 11.3 community resources .......................................... 29 11.4 trademarks ........................................................... 29 11.5 electrostatic discharge caution ............................ 29 11.6 glossary ................................................................ 29 12 mechanical, packaging, and orderable information ........................................................... 30 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes january 2018 * initial release
3 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions mol package 59-pin bqfn top view 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 28 29 33 30 31 32 34 35 36 37 38 39 40 42 43 44 45 46 47 48 49 50 51 52 vinbp bp6 bp6_rt n bp3 vin vin vin pgnd pgnd vout vout vout pgnd pgnd pgnd pgnd pgnd dnc dnc vout ph phph ph ph dn c dnc dnc dnc dnc dnc bp_rtn pgood ishare vshare vs+ vs- diffo fb dnc comp agnd sync en rt rt_sel phph 53 54 56 vout ph vin pgnd nc nc pgnd vout 55 57 pgnd 58 pgnd 59 pgnd 41 27 1 15
4 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions pin i/o description name no. agnd 10 g analog ground for the controller circuitry. this pin is internally connected to pgnd. bp_rtn 51 g return path for vinbp and bp3. this pin is internally connected to pgnd, pad 59. bp3 47 o output of the internal 3.3-v regulator. bypass this pin with a minimum of 2.2- f to bp_rtn. can be used as a pullup termination voltage for pgood and en signals. bp6 49 o output of the internal 6.5-v regulator that powers the driver stage of the device. bypass this pin with a minimum of 2.2 f to bp6_rtn. bp6_rtn 48 g power ground return path for bp6 bypass cap. comp 9 o output of the error amplifier. diffo 6 o output of the remote sense differential amplifier. this provides remote sensing for output voltage reporting and the voltage control loop. dnc 8, 16, 17, 18, 19, 20, 21, 30, 31 ? do not connect. do not connect these pins to agnd, pgnd to a different dnc pin or to any other voltage. these pins are connected to internal circuitry. each pin must be soldered to an isolated pad. en 12 i en pin. to enable, pull this pin up to a voltage less than 5.5 v using a 10-k resistor. pull this pin to agnd to disable the device. fb 7 i feedback pin for the control loop. ishare 2 i current sharing signal for parallel operation. nc 1, 15 ? not connected. these pins are internally isolated from any signal and all other pins. each pin must be soldered to a pad on the pcb. these pins can be left isolated, or connected to agnd or pgnd. pgnd 32, 33, 34, 35 36, 42, 43, 54 56, 57, 58, 59 g power ground of the device. this is the return current path for the power stage of the device. connect these pins to the bypass capacitors associated with vin and vout. connect pads 56, 57, 58, and 59 to the pcb ground planes using multiple vias for optimal thermal performance. all pins must be connected together externally with a copper plane or pour directly under the device. pgood 52 o power-good indicator. this pin is an open-drain output, which asserts low during any fault conditions. requires a pullup resistor. ph 22, 23, 24, 25 26, 27, 28, 29 o phase switch node. do not connect any external components to these pins or tie them to a pin of a different function. rt 13 i frequency-setting resistor. to operate the device at its default switching frequency, make no connection to this pin. to operate at a different switching frequency, connect a resistor from this pin to agnd. rt_sel 14 i rt resistor select. to operate the device at its default switching frequency, connect this pin to agnd. to operate at a different switching frequency, let this pin float. sync 11 i/o frequency synchronization pin. in a stand-alone application or as the master device in a parallel configuration, the sync pin is configured as a sync-in pin and power conversion is synchronized to the rising edge of a 50% duty cycle external clock applied to this pin. for a slave device in a parallel configuration, power conversion is synchronized to the falling edge of the incoming clock. vin 44, 45, 46, 53 i input switching voltage pins. these pins supply voltage to the power switches of the converter. vinbp 50 i input power to the controller circuitry. bypass this pin with a minimum of 1- f to bp_rtn. this pin is internally connected to vin. vout 37, 38, 39, 40, 41, 55 o output voltage. these pins are connected to the internal output inductor. connect these pins to the output load and connect external bypass capacitors between these pins and pgnd. vs+ 4 i positive input of the remote sense amplifier. connect this pin to vout at the load for best voltage regulation. do not let this pin float. vs ? 5 i negative input of the remote sense amplifier. connect this pin to ground at the load for best voltage regulation. do not let this pin float. vshare 3 i/o voltage sharing signal for parallel operation.
5 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) parameter min max unit input voltage vin ? 0.3 18 v vin < 2-ms transient 19 vin ? ph (vin to ph differentially) ? 0.3 25 fb ? 0.3 3.6 vs+, vs ? , rt, en, sync, pgood, ishare, rt_sel ? 0.3 7 bp6_rtn, bp_rtn, agnd ? 0.3 0.3 output voltage ph ? 1 25 v ph < 100-ns transient ? 5 25 bp6, comp, diffo, vshare ? 0.3 7 bp3 ? 0.3 3.6 operating ic junction temperature, t j ? 40 150 c storage temperature, t stg ? 55 150 c mechanical shock 500 g mechanical vibration 10 g (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 500 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 1500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) parameter min nom max unit input voltage vin 4.5 12 15 v sync 3.3 6.5 en, pgood pullup voltage 3.3 5.5 output voltage v out 0.5 2 v output current i out 0 35 a frequency 300 500 1000 khz temperature operating ambient temperature ? 40 105 c operating ic junction temperature ? 40 125 c
6 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for more information about thermal metrics, see the semiconductor and ic package thermal metrics application report. (2) the junction-to-ambient thermal resistance, r ja , applies to devices soldered directly to a 100 mm 100 mm, 6-layer pcb with 2 oz. copper and natural convection cooling. additional airflow reduces r ja . (3) the junction-to-top characterization parameter, jt , estimates the junction temperature, t j , of a device in a real system, using a procedure described in jesd51-2a (section 6 and 7). t j = jt pdis + t t ; where pdis is the power dissipated in the device and t t is the temperature of the top of the device. (4) the junction-to-board characterization parameter, jb , estimates the junction temperature, t j , of a device in a real system, using a procedure described in jesd51-2a (sections 6 and 7). t j = jb pdis + t b ; where pdis is the power dissipated in the device and t b is the temperature of the board 1mm from the device. 6.4 thermal information thermal metric (1) TPSM846C24 unit mol (qfn) 59 pins r ja junction-to-ambient thermal resistance (2) 8.7 c/w jt junction-to-top characterization parameter (3) 0.9 c/w jb junction-to-board characterization parameter (4) 4.3 c/w (1) specified by design. (2) the stated limit of the set-point tolerance includes the tolernace of both the internal voltage reference and the internal adjustment resistor. the overall output voltage tolerance is affected by the tolerance of the external r set resistor. 6.5 electrical characteristics over ? 40 c to 105 c free-air temperature range, v in = 12 v, v out = 1.2 v, i out = i out(max) , ? sw = 500 khz, c in1 = 4 22 f, 25 v, 1210 ceramic; c in2 = 2 330 f, 25 v, electrolytic bulk; c out1 = 4 47 f, 6.3 v, 1210 ceramic; c out2 = 2 470 f, 6.3 v, polymer bulk (unless otherwise noted) parameter test conditions min typ max unit input voltage (v in ) v in input voltage over i out range 4.5 15 v v in_uvlo v in undervoltage lock out v in rising 4.5 v v in falling 4 i vin input operating current en = 0 v 7.7 12 ma output voltage (v out ) v out v out adjustable range (1) over i out range 0.5 2 v setpoint voltage tolerance r set = not loaded, t j = 25 c, i out = 0 a ? 1% 1% r set = 10 k , 1%, t j = 25 c, i out = 0 a (2) ? 1.5% 1.5% temperature variation 0 c < t j < 85 c, i out = 0 a (1) ? 0.5% 0.5% ? 40 c < t j < 125 c, i out = 0 a (1) ? 1% 1% line regulation 4.5 v < v in < 15 v, i out = 0 a 0.05% load regulation over i out range, using remote sense 0.2% output voltage ripple 20-mhz bandwidth 13 mv output current i out output current natural convection. see soa graph for derating over temperature. 0 35 a overcurrent threshold 42 a i oc(acc) overcurrent accuracy ? 15% 15% i sh(acc) output current share accuracy (i out1 ? i out2 ) i total , i out 20 a per module (1) ? 15% 15% (i outx ? i total ) 2, i out < 20 a per module (1) ? 3 3 a soft start / stop t sstart internal soft-start time 3 ms t sstop internal soft-stop time 3 ms enable (en) v en enable threshold voltage enable high voltage 1.3 v enable low voltage 0.8 v hysteresis on enable 170 mv
7 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over ? 40 c to 105 c free-air temperature range, v in = 12 v, v out = 1.2 v, i out = i out(max) , ? sw = 500 khz, c in1 = 4 22 f, 25 v, 1210 ceramic; c in2 = 2 330 f, 25 v, electrolytic bulk; c out1 = 4 47 f, 6.3 v, 1210 ceramic; c out2 = 2 470 f, 6.3 v, polymer bulk (unless otherwise noted) parameter test conditions min typ max unit (3) functionality verified. limits specified at internal ic test. (4) specified by design. (5) the minimum required output capacitance consists of 4 47- f ceramic capacitors and 2 470- f, 10-m esr (5 m equivalent). (6) the proper frequency compensation network values are determined by the total amount of output capacitance (see setting the compensation network ). (7) the maximum esr refers to the combined equivalent esr of all non-ceramic output capacitors. for example, two 10-m esr capacitors have a combined equivalent esr of 5 m . power good (pgood) and overvoltage / undervoltage threshold (3) pgood pgood output low voltage v in = 4 v, v out = 0 v, i pgood = 5 ma 0.3 v v in = 0 v, i pgood = 80 a 0.8 pgood thresholds v out rising good 95 %v o fault 112 %v o v out falling good 105 %v o fault 88 %v o performance efficiency (4) v in = 12 v, i out = 25 a v out = 0.8 v 83% v out = 1.2 v 87% v out = 1.8 v 90% v in = 5 v, i out = 25 a v out = 0.8 v 84% v out = 1.2 v 88% v out = 1.8 v 91% transient response (4) 10 a / s load step from 25% to 75% of i out(max) , c out = 1000 f, rc = 1 k , cc = 1 nf v out over/undershoot 60 mv recovery time 60 s 10 a / s load step from 25% to 75% of i out(max) , c out = 2000 f, rc = 665 , cc = 1.5 nf v out over/undershoot 40 mv recovery time 60 s 10 a / s load step from 25% to 75% of i out(max) , c out = 4000 f, rc = 499 , cc = 2.2 nf v out over/undershoot 27 mv recovery time 60 s internal ldo (bp6, bp3) (3) v bp6 bp6 regulator output voltage 7.5v v in 15 v, switching 5.85 6.4 6.95 v v bp6 (do) dropout voltage (v vin ? v bp6 ), v in = 4.5 v, switching 400 mv v bp3 bp3 regulator output voltage v in 4.5 v 3 3.2 3.4 v thermal shutdown t sd junction thermal shutdown temperature 145 160 c t hyst thermal shutdown hysteresis 25 c capacitance c in external input capacitance ceramic 88 f non-ceramic 660 c out external output capacitance ceramic (5) 188 f non-ceramic (5) 940 4000 (6) esr (7) 5 m
8 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) specified by design. (2) functionality verified. limits specified at internal ic test. 6.6 switching characteristics over ? 40 c to 105 c free-air temperature range, v in = 12 v,v out = 1.2 v, i out = i out(max) , ? sw = 500 khz, c in1 = 4 22- f, 25-v, 1210 ceramic; c in2 = 2 330- f, 25-v, electrolytic bulk; c out1 = 4 47- f, 6.3-v, 1210 ceramic; c out2 = 2 470- f, 6.3-v, polymer bulk (unless otherwise noted) parameter test conditions min typ max unit oscillator ? sw switching frequency factory default setting. r rt = open; rt_sel grounded 425 500 575 khz r rt = 68.1 k ? , 1%; rt_sel open 255 300 345 r rt = 20.0 k ? , 1%; rt_sel open 850 1000 1150 adjustment range 300 1000 pwm t on-min minimum on-time (1) 50 100 ns t off-min minimum off-time (1) ? sw = 1 mhz 515 560 ns synchronization v ih(sync) high-level input voltage (2) 2.2 v v il(sync) low-level input voltage (2) 0.8 v d sync sync input duty cycle ? sw = 300 khz to 1 mhz 50% ? sync sync frequency range 300 1000 khz
9 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.7 typical characteristics (v in = 12 v) v in = 12 v, t a = 25 c, f sw = 500 khz (unless otherwise specified). safe operating area curves were measured using a texas instruments evaluation module (evm). v in = 12 v f sw = 500 khz figure 1. efficiency vs output current v in = 12 v f sw = 500 khz figure 2. power dissipation vs output current v in = 12 v f sw = 500 khz figure 3. voltage ripple vs output current v in = 12 v v out = 0.8 v f sw = 500 khz figure 4. safe operating area v in = 12 v v out = 1.2 v f sw = 500 khz figure 5. safe operating area v in = 12 v v out = 1.8 v f sw = 500 khz figure 6. safe operating area output current (a) efficiency (%) 0 5 10 15 20 25 30 35 55 60 65 70 75 80 85 90 95 100 d001 1.8 v 1.2 v 0.8 v output current (a) power dissipation (w) 0 5 10 15 20 25 30 35 0 2 4 6 8 10 d002 1.8 v 1.2 v 0.8 v output current (a) output voltage ripple (mv) 0 5 10 15 20 25 30 35 6 8 10 12 14 16 18 20 d003 1.8 v 1.2 v 0.8 v output current (a) ambient temperature (c) 0 5 10 15 20 25 30 35 25 35 45 55 65 75 85 95 105 115 d007 400lfm 200lfm 100lfm nat conv output current (a) ambient temperature (c) 0 5 10 15 20 25 30 35 25 35 45 55 65 75 85 95 105 115 d009 400lfm 200lfm 100lfm nat conv output current (a) ambient temperature (c) 0 5 10 15 20 25 30 35 25 35 45 55 65 75 85 95 105 115 d008 400lfm 200lfm 100lfm nat conv
10 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.8 typical characteristics (v in = 5 v) v in = 5 v, t a = 25 c, f sw = 500 khz (unless otherwise specified). safe operating area curves were measured using a texas instruments evaluation module (evm). v in = 5 v f sw = 500 khz figure 7. efficiency vs output current v in = 5 v f sw = 500 khz figure 8. power dissipation vs output current v in = 5 v f sw = 500 khz figure 9. voltage ripple vs output current v in = 5 v v out = 0.8 v f sw = 500 khz figure 10. safe operating area v in = 5 v v out = 1.2 v f sw = 500 khz figure 11. safe operating area v in = 5 v v out = 1.8 v f sw = 500 khz figure 12. safe operating area output current (a) ambient temperature (c) 0 5 10 15 20 25 30 35 25 35 45 55 65 75 85 95 105 115 d011 400lfm 200lfm 100lfm nat conv output current (a) ambient temperature (c) 0 5 10 15 20 25 30 35 25 35 45 55 65 75 85 95 105 115 d012 400lfm 200lfm 100lfm nat conv output current (a) power dissipation (w) 0 5 10 15 20 25 30 35 0 2 4 6 8 10 d005 1.8 v 1.2 v 0.8 v output current (a) efficiency (%) 0 5 10 15 20 25 30 35 55 60 65 70 75 80 85 90 95 100 d004 1.8 v 1.2 v 0.8 v output current (a) ambient temperature (c) 0 5 10 15 20 25 30 35 25 35 45 55 65 75 85 95 105 115 d010 400lfm 200lfm 100lfm nat conv output current (a) output voltage ripple (mv) 0 5 10 15 20 25 30 35 6 8 10 12 14 16 18 20 d006 1.8 v 1.2 v 0.8 v
11 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the TPSM846C24 device is a 35-a, high-performance, synchronous buck power module, enabling high-power density and minimal pcb area. this device implements the industry-standard fixed switching frequency, voltage- mode control with input feed-forward topology that responds instantly to input voltage change. the tspm846c24 device can be synchronized to the external clock to eliminate beat noise and reduce emi and emc. monotonic prebias capability eliminates concerns about damaging sensitive loads. two TPSM846C24 devices can be paralleled together to provide up to 70-a load. current sensing for overcurrent protection and current sharing between two devices are implemented by sampling a small portion of the power-stage current which provides accurate information independent of the device temperature. 7.2 functional block diagram vin pgnd vout TPSM846C24 power stage and driver control oscillator bp6 linear regulators bp3 vinbp ph 10 k o agnd en analog inputs and interface pgood diffo fb comp vshare ishare vs+ vs- remote sense amplifier comp + vref current share vref temp sensing bp6_rtn bp_rtn sync rt rt_sel 40.2 k o copyright ? 2018, texas instruments incorporated
12 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3 feature description 7.3.1 minimum capacitance requirements for proper operation, the minimum required input capacitance network consists of four 22- f (or two 47- f) ceramic capacitors plus a 330- f bulk capacitor. see capacitors c1 thru c5 in figure 13 . place the ceramic capacitors as close as possible to the vin pins. the ground return path of the capacitors must connect to pgnd pins 42, 43, 54, and 59 of the TPSM846C24. the minimum required output capacitance network consists of four 47- f (or two 100- f) ceramic capacitors plus two 470- f, low-esr polymer capacitors. see capacitors c10 thru c15 in figure 13 . the combined esr of the polymer capacitors must not be greater than 5 m . place the ceramic capacitors as close as possible to the vout and pgnd pins of the module. this minimum network insures good transient response and minimal ripple amplitude. the total amount of output capacitance determines the values of the frequency compensation network. for more details see the setting the compensation network section. additionally, the analog power path (vinbp) requires its own bypass network consisting of a 10-nf ceramic capacitor (c8 in figure 13 ) and 1- f ceramic capacitor (c7 in figure 13 ) connected directly across pins 50 and 51 of the module. for proper operation, the two internal power supply rails of the module must also be bypassed. the 6.5-v rail (bp6) requires a 4.7- f ceramic capacitor (c6 in figure 13 ) placed across pins 48 and 49 of the module with short, direct traces. the 3.3-v rail (bp3) requires a 2.2- f ceramic capacitor (c9 in figure 13 ) placed very close to pins 47 and 51. figure 13. required capacitor schematic bp3 bp6 bp6_rtn 49 47 48 vin 44 vin 53 vin 45 vin 46 pgnd 43 pgnd 54 pgnd 51 bp_rtn 42 vout 37 vout 38 vout 39 vout 40 vout 41 vout 55 vs+ 4 vs- 5 pgnd 32 pgnd 33 pgnd 34 pgnd 35 pgnd 36 pgnd 56 pgnd 57 pgnd 58 50 vinbp 59 pgnd c2 c3 c4 TPSM846C24 c6 22 f 22 f 22 f 4.7 f c5 22 f c7 1 f c8 10 nf c9 2.2 f c10 47 f c11 47 f c12 47 f c13 47 f c1 330 f + 470 f + c14 470 f + c15 vout pgnd vin pgnd copyright ? 2017, texas instruments incorporated
13 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 7.3.2 setting the compensation network the TPSM846C24 requires an external series resistor and capacitor compensation network to be connected between the diffo pin (pin 6) and the fb pin (pin 7). these are r comp and c comp in figure 14 . the value of these components is determined by the total amount of output capacitance and the switching frequency. ti recommends only ceramic and low-esr, polymer-type capacitors are. place these components as close as possible to the module and away from noisy signal traces. suggested values for r comp and c comp for some typical values of output capacitance are given in table 1 . final values should be determined by testing system stability using standard power supply evaluation techniques. figure 14. compensation components table 1. recommended compensation components total c out ( f) switching frequency typical c out 300 - 400 khz 400 - 600 khz 600 - 1000 khz min max r comp c comp r comp c comp r comp c comp ceramic polymer 1000 1500 1.0 k 1000 pf 665 1500 pf 499 2200 pf 4 47 f 2 470 f 1500 3000 665 1500 pf 499 2200 pf 249 4700 pf 4 47 f 4 470 f 3000 5000 499 2200 pf 249 4700 pf 124 6800 pf 4 47 f 4 1000 f diffo 6 fb 7 TPSM846C24 r comp c comp copyright ? 2017, texas instruments incorporated
14 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) 50% load step at 2.5 a/ s. (2) the combined equivalent esr of all non-ceramic output capacitance must be 5 m . 7.3.3 transient response the TPSM846C24 is designed to have an exceptional output voltage transient response to output current load steps. table 2 shows the voltage deviation for several transient conditions. table 2. output voltage transient response c in = 4 22 f ceramic, 2x 330 f electrolytic v out (v) v in (v) f sw (khz) r comp c comp c out voltage (1) deviation (mv) ceramic non-ceramic (2) 0.6 5 500 499 2200 pf 4 47 f 4 470 f 33 500 249 4700 pf 4 47 f 4 1000 f 22 12 500 249 4700 pf 4 47 f 4 470 f 24 750 124 6800 pf 4 47 f 4 1000 f 18 0.8 5 500 499 2200 pf 4 47 f 4 470 f 37 750 124 6800 pf 4 47 f 4 1000 f 19 12 500 499 2200 pf 4 47 f 4 470 f 33 500 249 4700 pf 4 47 f 4 1000 f 20 1.0 5 500 665 1500 pf 4 47 f 2 470 f 48 500 499 2200 pf 4 47 f 4 470 f 38 500 249 4700 pf 4 47 f 4 1000 f 26 12 500 665 1500 pf 4 47 f 2 470 f 41 500 499 2200 pf 4 47 f 4 470 f 32 750 499 2200 pf 4 47 f 2 470 f 26 1.2 5 500 665 1500 pf 4 47 f 2 470 f 38 750 499 2200 pf 4 47 f 2 470 f 34 12 500 665 1500 pf 4 47 f 2 470 f 39 500 499 2200 pf 4 47 f 4 470 f 35 2 5 300 1.0 k 1000 pf 4 47 f 2 470 f 50 500 665 1500 pf 4 47 f 2 470 f 38 12 300 1.0 k 1000 pf 4 47 f 2 470 f 57 500 665 1500 pf 4 47 f 2 470 f 42
15 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.4 setting the output voltage the TPSM846C24 output voltage adjustment range is 0.5 v to 2 v. the adjustment method requires a resistor, r set , connected between the fb pin and agnd as shown in figure 15 . equation 1 can be used to calculate the r set value for a given output voltage, v out . additionally, the r set value can be selected from table 3 . figure 15. rset resistor (1) table 3. standard r set resistor values v out (v) r set (k ? ) v out (v) r set (k ? ) 0.5 open 1.3 6.19 0.6 49.9 1.4 5.49 0.7 24.9 1.5 4.99 0.8 16.5 1.6 4.53 0.9 12.4 1.7 4.12 1 10 1.8 3.83 1.1 8.25 1.9 3.57 1.2 7.15 2.0 3.32 7.3.5 differential remote sense the TPSM846C24 device implements a differential remote-sense amplifier to provide excellent load regulation by cancelling ir-drop in high-current applications. the vs+ and vs ? pins must be kelvin-connected to the output capacitor bank directly at the load, and routed back to the device as a tightly coupled differential pair. ensure that these traces are isolated from fast switching signals and high current paths on the final pcb layout, as these can add differential-mode noise. diffo 6 fb 7 TPSM846C24 r comp c comp agnd 10 r set copyright ? 2017, texas instruments incorporated 5 r set = (k ) (v out 0.5)
16 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.6 switching frequency and synchronization 7.3.6.1 setting the switching frequency the TPSM846C24 is set to a default switching frequency of 500 khz. to operate the TPSM846C24 at the default switching frequency, connect the rt_sel pin (pin 14) to agnd and leave the rt pin (pin 13) open. to change the switching frequency, leave the rt_sel pin open, and connect a resistor from the rt pin (r rt ) to agnd. use equation 2 to calculate the r rt resistor value. (2) the TPSM846C24 devices are designed to operate from 300 khz to 1 mhz. 7.3.6.2 synchronization the TPSM846C24 device can synchronize to an external clock that is 20% of the free-running frequency set by r rt . it is required that the external clock waveform is a square wave with a duty cycle of 50%. 7.3.6.2.1 stand-alone device synchronization when power is applied, if no external clocking signal is present on the sync pin, the device operates at the switching frequency set by the internal or an external timing resistor. if an external clock signal that meets the specification of the synchronization section of the switching characteristics table is applied to the sync pin, the device synchronizes to the leading edge of the applied waveform. the rising edge of the ph node lags the rising edge of the clocking waveform by approximately 500 ns. the external clock must be a 50% duty-cycle square wave. the external clock frequency must be with 20% of the free-running frequency set by the r rt resistor. it is permissible for the sync signal to become active after the module has powered-up. if this is done, there is a small disturbance in the output voltage while the module locks to the sync clock. if the sync signal is lost during operation, the module quickly detects the loss and reverts to switching at the frequency set by the r rt resistor. a disturbance occurs in the output voltage upon loss of sync. 7.3.6.2.2 paralleled devices synchronization when two TPSM846C24 devices are paralleled, the sync pins of the master and the slave must be supplied with a 50% duty cycle clock signal at the desired switching frequency. the master device locks to the rising edge of the clock; the slave locks to the falling edge. the 50% duty cycle requirement insures the modules operate 180 out of phase to minimize ripple. both the master and slave module must have an r rt resistor present whose value sets a switching frequency within 20% of the sync clock frequency. see the parallel application section of the datasheet for more information when paralleling devices. in rt sw 18290 120 v r k f khz u :
17 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.7 prebiased output start-up the TPSM846C24 devices prevent current from being discharged from the output during start-up when a prebiased output condition exists. if the output is prebiased, no ph pulses occur until the internal soft-start voltage rises above the error-amplifier input voltage (fb pin). as soon as the soft-start voltage exceeds the error- amplifier input, and ph pulses start. the device limits synchronous rectification after each ph pulse with a narrow on-time. the on-time of the low-side mosfet slowly increases on a cycle-by-cycle basis until 128 pulses have been generated and the synchronous rectifier runs fully complementary to the high-side mosfet. this approach prevents the sinking of current from a prebiased output, and ensures the output-voltage start-up and ramp-to-regulation sequences are smooth and monotonic. if the prebias voltage is close to or exceeds the v out setpoint voltage, the mandatory 128 switching cycles, as previously described , may induce a non-monotonic dip in the output voltage. the output voltage quickly recovers to the setpoint value once the 128 cycle interval is completed. these devices respond to a prebiased output overvoltage condition immediately upon vin powered up and when the bp6 regulator voltage is above the bp6 uvlo of 3.73 v (typical). 7.3.8 power-good (pgood) indicator the TPSM846C24 has a built-in power-good signal (pgood) which indicates whether the output voltage is within its regulation range. the pgood pin is an open drain output that requires a pullup resistor to a voltage source of 5.5 v or less. the recommended pullup resistor value is between 10 k and 100 k . once the output voltage rises above 95% of the set voltage, the pgood pin rises to the pullup voltage level. the pgood pin is pulled low when the output voltage drops lower than 88% or rises higher than 112% of the nominal set voltage. the pgood signal can be connected to the en pin of a different device to provide additional controlled turnon and turnoff sequencing. the pgood signal is pulled low when the fb pin is prebiased to higher than 5% above the regulation level. this level of prebias is unusual and it is beneficial to flag a warning in this situation. note the presence of a pullup voltage at the pgood pin before input voltage is applied, may cause the pgood pin to be pulled above a logic low voltage level. this is due to the limited pulldown capability in an un-powered condition. if this is not desired, increase the pullup resistance or reduce the external pullup supply voltage. 7.3.9 linear regulators bp3 and bp6 the TPSM846C24 device has two onboard linear regulators to provide suitable power for the internal circuitry of the device. bypass the bp3 and bp6 pins externally for the converter to function properly. the bp3 pin requires a minimum of 2.2 f of capacitance connected to bp_rtn. the bp6 pin requires a minimum 4.7 f of capacitance connected to bp6_rtn. the use of the internal regulators to power other circuits is not recommended because the loads placed on the regulators might adversely affect operation of the controller. note place bypass capacitors as close as possible to the device pins, with a minimum return loop back to ground and keep the return loop away from fast switching voltage and main current path. for more information, see the layout section. poor bypassing can degrade the performance of the regulator.
18 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.10 parallel application two TPSM846C24 devices can be paralleled for increased output current up to 70 a. multiple connections must be made between the paralleled devices and the component selection is slightly different than for a stand-alone TPSM846C24 device. figure 16 shows a typical schematic for two TPSM846C24 devices in parallel. parallel operation can be evaluated using the TPSM846C24devm-007 evaluation board. figure 16. TPSM846C24 parallel v in v out TPSM846C24 vin pgnd vout vs+ diffo pgnd vs- agnd fb vshare ishare pgnd en sync rt_sel bp3 TPSM846C24 vin pgnd vout vs+ diffo pgnd vs- agnd fb vshare ishare pgnd en sync rt_sel bp3 master slave copyright ? 2017, texas instruments incorporated en 500-khz clock 50% duty
19 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.11 parallel operation to operate two TPSM846C24 devices in parallel, one of the devices must act as the master and the other act as a slave. to configure one of the devices as the slave device, connect a 1-k resistor between the device fb pin and bp3 pin. additionally, the sync, vshare, and ishare pins of both devices must be connected as shown in figure 16 . both devices share the same vshare voltage. essentially, the internal comp voltage is shared between the two devices by connecting the vshare pin of each device together. by connecting the ishare pins of each device, the sensed current in each phase is compared, then the error current is added into the internal comp. the resulting voltage is compared with the pwm ramp to generate the pwm pulse. this current sharing loop maintains the current balance between devices. in addition to sharing the same internal comp voltage, the vshare pin is also used for fault communication between the loop master and slave devices. the vshare pin voltage is pulled low if any device encounters any fault conditions so that the other device sharing vshare pin is alerted and stops switching accordingly. when configured for parallel operation, the sync pins of the master and the slave must be supplied with a 50% duty cycle clock signal at the desired switching frequency. the master device locks to the rising edge of the clock; the slave locks to the falling edge. the 50% duty cycle requirement insures the modules operate 180 out of phase to minimize ripple. both the master and slave module must have an r rt resistor present whose value sets a switching frequency within 20% of the sync clock frequency. an optional high-frequency capacitor can be added between the vshare pin and ground in noisy systems, but the capacitance must not exceed 10 pf. if operating conditions result in an on-time pulse width of 150 ns, jitter may be observed on the master and slave ph pins. the addition of a 10-k resistor in series with the ishare connection between the devices helps to reduce, but may not eliminate, the jitter. 7.3.12 overtemperature protection an internal temperature sensor based off the bandgap reference protects the TPSM846C24 device from thermal runaway. the internal thermal shutdown threshold, t sd , is fixed at 145 c (typical). when the device senses a temperature above t sd , power conversion stops until the sensed junction temperature decreases by the amount of the thermal shutdown hysteresis, t hyst (25 c typical). the response to an over temperature fault is to shut down and then restart. 7.3.13 overcurrent protection both low-side overcurrent and high-side short circuit protection are implemented. the low-side mosfet average current is compared to the fault threshold. high-side pulses are terminated on a cycle-by-cycle basis whenever the current through the high-side mosfet exceeds the fixed short-circuit threshold. when either a low-side overcurrent or high-side short-circuit threshold is exceeded in a switching cycle, a counter is incremented. if no overcurrent condition is detected in a switching cycle, the counter is decremented. if the counter counts to three, an overcurrent fault condition is declared, and the output shuts down and restarts after approximately 21 ms. 7.3.14 output overvoltage and undervoltage protection the TPSM846C24 device includes both output-overvoltage protection and output undervoltage protection capability by comparing the fb pin voltage to internal pre-set voltages. if the fb pin voltage rises above the output overvoltage-protection threshold, the device terminates normal switching and turns on the low-side mosfet to discharge the output capacitor and prevent further increases in the output voltage. the device declares an ov fault and enters continuous-restart-hiccup mode. the TPSM846C24 device responds to the output overvoltage condition immediately upon vin powered up and bp6 regulator voltage above its own uvlo of 3.73 v (typical). if the fb pin voltage falls below the undervoltage protection level after soft start has completed, the device terminates normal switching and forces both the high-side and low-side mosfets off, and begins a hiccup time- out delay prior to restart.
20 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4 device functional modes 7.4.1 active mode the TPSM846C24 device operates in continuous conduction mode (ccm) at a fixed frequency, regardless of the output current. for the first 128 switching cycles, the low-side mosfet on-time is slowly increased to prevent excessive current sinking in the event the device is started with a prebiased output. following the first 128 clock cycles, the low-side mosfet and the high-side mosfet on-times are fully complementary. 7.4.2 shutdown mode the TPSM846C24 uses the en pin to enable or disable power conversion. the en pin must be pulled high to allow power conversion. the en pin provides electrical on and off control for the TPSM846C24. when the en pin voltage is below the en low threshold, the device is in shutdown mode. in shutdown mode the stand-by current is 7.7 ma typically with v in = 12 v. the TPSM846C24 also employs undervoltage lockout protection. if v in is below the uvlo level, the output of the regulator is turned off.
21 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 typical application the TPSM846C24 is a highly-integrated, synchronous step-down dc-dc power module. the TPSM846C24 converts a higher dc-input voltage to a lower dc-output voltage, with a maximum output current of 35 a. use the following design procedure to select key component values and select the appropriate features. figure 17. typical application schematic bp3 bp6 bp6_rtn pgood 49 47 48 vin 44 vin 53 vin 45 vin 46 52 pgnd 43 pgnd 54 pgnd 51 bp_rtn 42 sync 2 ishare 3 vshare diffo 6 fb 7 comp 9 11 en 12 dnc 16 dnc 17 dnc 18 dnc 19 dnc 20 ph 24 ph 25 ph 26 ph 27 ph 28 vout 37 ph 29 vout 38 vout 39 vout 40 vout 41 vout 55 vs+ 4 vs- 5 pgnd 32 pgnd 33 pgnd 34 pgnd 35 pgnd 36 pgnd 56 pgnd 57 pgnd 58 rt 13 rt_sel 14 agnd 10 nc 15 50 vinbp nc 1 59 pgnd c2 c3 c4 u1 TPSM846C24mol c6 22 f 22 f 22 f 4.7 f c5 22 f c7 1 f c8 10 nf c9 2.2 f 8 dnc 21 dnc 30 dnc 31 dnc 10 k r1 10 k r2 r comp r set c comp c10 47 f c11 47 f c12 47 f c13 47 f c1 330 f + 470 f + c14 470 f + c15 vout pgnd vin pgnd pgood en ph 22 ph 23 copyright ? 2017, texas instruments incorporated
22 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 8.1.1 design requirements for this design example, use the parameters listed in table 4 and follow the design procedures below. table 4. design parameters design parameter value input voltage v in 12 v typical output voltage v out 1.2 v output current rating 35 a key care-abouts small footprint, high efficiency, pgood signal 8.1.2 detailed design procedure 8.1.2.1 custom design with webench ? tools click here to create a custom design using the TPSM846C24 device with the webench ? power designer. 1. start by entering the input voltage (v in ), output voltage (v out ), and output current (i out ) requirements. 2. optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. compare the generated design with other possible solutions from texas instruments. the webench power designer provides a customized schematic along with a list of materials with real-time pricing and component availability. in most cases, these actions are available: ? run electrical simulations to see important waveforms and circuit performance ? run thermal simulations to understand board thermal performance ? export customized schematic and layout into popular cad formats ? print pdf reports for the design, and share the design with colleagues get more information about webench tools at www.ti.com/webench . 8.1.2.2 setting the output voltage the output voltage of the TPSM846C24 is designed to be set by the r set resistor. use equation 3 to calculate the r set resistor value. (3) to set the output voltage to 1.2 v, using equation 3 , the calculated value of r set is 7.14 k . the nearest e96 resistor value is 7.15 k 8.1.2.3 input and output capacitance the minimum required input capacitance network consists of four 22- f (or two 47- f) ceramic capacitors plus a 330- f bulk capacitor. the minimum required output capacitance network consists of four 47- f (or two 100- f) ceramic capacitors plus two 470- f, low esr polymer capacitors. the combined esr of the polymer capacitors must not be greater than 5 m . additional input and output capacitors can be added to improve ripple or transient response. in this design example, the minimum required input and output capacitance is used. 8.1.2.4 selecting the compensation components the TPSM846C24 requires an external series resistor and capacitor compensation network to be connected between the diffo pin (pin 6) and the fb pin (pin 7). the value of these components is determined by the total amount of output capacitance. in this design example, the value of r comp and c comp is selected from table 1 based on the total amount of output capacitance of 1120 f. r comp = 1 k and c comp = 1000 pf. 5 r set = (k ) (v out 0.5)
23 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.1.2.5 setting the switching frequency the TPSM846C24 is set to a default switching frequency of 500 khz. to operate the TPSM846C24 at the default switching frequency, connect the rt_sel pin (pin 14) to agnd and leave the rt pin (pin 13) open. in this design example, the switching frequency is selected to operate at the default switching frequency of 500 khz by connecting rt_sel pin to agnd and the r rt resistor is left open. 8.1.2.6 power good (pgood) applications requiring voltage rail sequencing can benefit from the pgood signal present with the TPSM846C24. the pgood pin is an open-drain output. when the output voltage is typically between 95% and 105% of the setpoint, the pgood pin pulldown is released and the pin floats, requiring an external pullup resistor for a high signal. a 10-k pullup resistor is placed between the pgood pin and the bp3 rail. 8.1.2.7 on/off control (en) the en signal is used to turn the power conversion function of the module on and off. the en signal is an active high signal; that is, the en pin must be pulled high for power conversion to occur. the en pin requires an external pullup resistor for a high signal. a 10-k pullup resistor is placed between the en pin and the bp3 rail 8.1.3 application curves v in = 12 v v out = 1.2 v i out = 10 a figure 18. start-up waveforms v in = 12 v v out = 1.2 v i out = 10 a figure 19. shut-down waveform
24 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 power supply recommendations the TPSM846C24 device is designed to operate from an input voltage supply between 4.5 v and 15 v. this supply must be well regulated. these devices are not designed for split-rail operation. proper bypassing of input supplies and internal regulators is also critical for noise performance, as is pcb layout and grounding scheme. see the recommendations in the layout section. 10 layout 10.1 layout guidelines layout is critical for good power-supply design. figure 20 and figure 21 show top-side and bottom-side pcb- layout configuration for recommended component placement. additional power, ground and signal layers are present in any pcb design. a list of pcb layout considerations using these devices is listed as follows: ? place the input bypass capacitors as close as physically possible to the vin and pgnd pins. additionally, a high-frequency bypass capacitor on the vin pins can help reduce switching spikes. this capacitor can be placed on the bottom side of the pcb directly underneath the device to keep a minimum loop. ? the bp6 bypass capacitor carries a large switching current for the gate driver. bypassing the bp6 pin to bp6_rtn with a low-impedance path is very critical to the stable operation of the TPSM846C24 device. place the bp6 high-frequency bypass capacitor as close as possible to the device pins 48 and 49. ? the vinbp and bp3 pins also require good local bypassing. place bypass capacitors as close as possible to the device pins and bp_rtn. poor bypassing on the vinbp and bp3 pins can degrade the performance of the device. ? place signal components as close as possible to the pins to which they are connected. these components include the feedback resistors and the rt resistor. keep these components away from fast switching voltage and current paths. terminate these components to agnd with a minimum return loop. ? route the vs+ and vs ? lines from the output capacitor bank at the load back to the device pins as a tightly coupled differential pair. these traces must be kept away from switching or noisy areas which can add differential-mode noise. ? use caution when routing of the sync, vshare and ishare traces for parallel configurations. the sync trace carries a rail-to-rail signal and must be routed away from sensitive analog signals, including the vshare, ishare, rt, and fb signals. the vshare and ishare traces must also be kept away from fast switching voltages or currents formed by the vin, ph, and bp6 pins.
25 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 10.2 layout example figure 20. pcb top-side layout recommendation figure 21. pcb bottom-side layout recommendation
26 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 10.3 package specifications TPSM846C24 value unit weight 3.92 grams flammability meets ul 94 v-o mtbf calculated reliability per bellcore tr-332, 50% stress, t a = 40 c, ground benign 26.6 mhrs 10.4 emi the TPSM846C24 is compliant with en55022 class a radiated emissions. figure 22 to figure 25 show typical examples of radiated emissions plots for the TPSM846C24. the emi plots were taken using an evm with a resistive load and input power was provided using a lead acid battery. all graphs show plots of the antenna in the horizontal and vertical positions. figure 22. radiated emissions 12-v input, 1.2-v output, 35-a load vertical antenna figure 23. radiated emissions 12-v input, 1.2-v output, 35-a load horizontal antenna
27 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated emi (continued) figure 24. radiated emissions 5-v input, 1.2-v output, 35-a load vertical antenna figure 25. radiated emissions 5-v input, 1.2-v output, 35-a load horizontal antenna
28 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 10.5 mounting and thermal profile recommendation proper mounting technique adequately covers the exposed thermal pad with solder. excessive heat during the reflow process can affect electrical performance. figure 26 shows the recommended reflow-oven thermal profile. proper post-assembly cleaning is also critical to device performance. refer to power module msl ratings and reflow ratings for more information. figure 26. recommended reflow-oven thermal profile table 5. recommended thermal profile parameters parameter min typ max unit ramp up and ramp down r ramp(up) average ramp-up rate, t s(max) to t p 3 c/s r ramp(down) average ramp-down rate, t p to t s(max) 6 c/s pre-heat t s preheat temperature 150 200 c t s preheat time, t s(min) to t s(max) 60 120 s reflow t l liquidous temperature 217 c t p peak temperature 260 c t l time maintained above liquidous temperature, t l 60 150 s t p time maintained within 5 c of peak temperature, t p 20 30 s t 25p total time from 25 c to peak temperature, t p 480 s time (s) temperature (c) t s(max) t s(min) t l t p t s 25 r ramp(up) r ramp(down) t 25p t p t l
29 TPSM846C24 www.ti.com slvse06 ? january 2018 product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 development support 11.1.1.1 custom design with webench ? tools click here to create a custom design using the TPSM846C24 device with the webench ? power designer. 1. start by entering the input voltage (v in ), output voltage (v out ), and output current (i out ) requirements. 2. optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. compare the generated design with other possible solutions from texas instruments. the webench power designer provides a customized schematic along with a list of materials with real-time pricing and component availability. in most cases, these actions are available: ? run electrical simulations to see important waveforms and circuit performance ? run thermal simulations to understand board thermal performance ? export customized schematic and layout into popular cad formats ? print pdf reports for the design, and share the design with colleagues get more information about webench tools at www.ti.com/webench . 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. webench is a registered trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
30 TPSM846C24 slvse06 ? january 2018 www.ti.com product folder links: TPSM846C24 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 14-feb-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPSM846C24molr active qfm mol 59 350 rohs (in work) & green (in work) call ti call ti -40 to 105 TPSM846C24 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
www.ti.com package outline c b 15.1 14.9 a 16.1 15.9 6.4 max 24x 0.8 2x 9.6 20x 0.8 2x 8 4x 2.85 0.05 4x 2.55 0.05 48x 0.5 0.3 .000 pkg 0 2.3 .000 pkg 0 2.9 0.3 5.5 1.31 3.6 5.6 .000 pkg 0 3.7 .000 pkg 0 5.45 5.1 4x 2.2 4x 3.2 2.6 4.27 3.3 2 1.1 1.24 48x 0.6 0.4 0.08 c (0.05) typ qfm - 6.4 mm max height mol0059a plastic quad flat module 4223441/c 08/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance. pin 1 index area seating plane 0.1 c a b 0.05 1 15 27 14 2 28 41 52 53 54 55 56 57 58 59 scale 0.800 thermal pad detail tolerance 0.05 53 54 55 56 57 58 59 pkg pkg
www.ti.com example board layout 48x (0.4) .000 pkg 0 .000 pkg 0 0.07 min all around 48x (0.5) 4x (2.55) 4x (2.85) (0.8) typ (r0.05) typ .000 pkg 0 ( )7.7 ( )3.7 ( )5.1 ( )5.45 ( )7.7 4x (2.2) 2x (0.35) 4x (3.2) (0.45) .000 pkg 0 ( )1.31 ( )3.6 ( )5.6 (4.27) (3.3) (1.24) (1.1) (2) (2.6) ( )2.3 ( )0.3 ( )2.9 ( )5.5 ( )7.2 4x ( )6.025 ( )7.2 4x ( )6.675 ( )0.1 ( )1.125 ( )3.575 ( )4.775 ( )4.9 ( )6.4 qfm - 6.4 mm max height mol0059a plastic quad flat module 4223441/c 08/2017 notes: (continued) 4. this package is designed to be soldered to the thermal pads on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). 5. vias are optional depending on application, refer to device data sheet. if any vias are implemented, refer to their locations shown on this view. it is recommended that vias under paste be filled, plugged or tented. land pattern example see next page for via dimensions scale: 6x metal under solder mask typ solder mask opening typ 1 2 14 15 16 26 27 28 32 46 52 53 54 55 56 57 58 59 copper keep-out area 4x 0.5 x 0.85 solder mask opening metal under solder mask solder mask details solder mask defined pads
www.ti.com example board layout .000 pkg 0 .000 pkg 0 .000 pkg 0 ( )3.7 4x ( )5.2 ( )6.675 ( )5.45 ( ) typ1.7 ( )3.3 ( )5.1 ( )7.3 .000 pkg 0 ( )0.3 ( )2.9 ( )5.5 8x ( )7.025 ( )6.025 ( )3.6 5x ( )2.4 ( )1.31 (0.8) typ (r0.05) typ ( )2.3 (1.3) typ ( ) typ1.7 ( 0.2) typ via 2x (0.75) 2x (1.088) 2x (0.938) 4x (1) (0.59) typ ( )5.6 qfm - 6.4 mm max height mol0059a plastic quad flat module 4223441/c 08/2017 land pattern example via detail scale: 10x solder mask opening typ 41 53 54 55 56 57 58 59 metal under solder mask typ solder mask opening typ
www.ti.com example stencil design .0000 .0000 48x (0.4) 48x (0.5) (0.8) typ (r0.05) typ 16x (1.26) 16x (1.14) .0000 ( )1.31 ( )3.6 ( )5.6 ( )7.2 ( )7.2 ( )2.89 ( )1.71 ( )0.29 ( )0.89 ( )2.31 ( )3.49 ( )4.91 ( )6.09 .0000 ( )0.795 ( )0.795 ( )3.027 ( )4.374 ( )6.224 ( )7.7 ( )7.7 8x ( )6.005 8x ( )7.345 8x ( )6.755 8x ( )5.295 16x (1.39) 16x (0.98) 2x (1.744) 2x (1.147) 2x (1.04) 2x (1.2) ( )4.125 ( )4.677 ( )6.075 2x (1.75) 2x (1.347) qfm - 6.4 mm max height mol0059a plastic quad flat module 4223441/c 08/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. solder paste example based on 0.125 mm thick stencil printed solder coverage by area under package pads 1,15,27 & 41: 76% pad 53: 79% pads 54 - 59: 77% scale: 8x 1 2 14 15 16 26 27 28 41 52 53 54 55 56 57 58 59 pkg pkg metal under solder mask typ solder mask opening typ
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